1. Field of the Invention
The present invention relates to a built-in test circuit, more particularly a serial interface device built-in test circuit capable of detecting command symbols to automatically compensate loopback latency.
2. Description of the Prior Art
In the development of personal computer systems and peripheral devices, bandwidth and speed requirements of the interconnect interface are increasing. Loads of conventional parallel interfaces are insufficiently. Therefore, serial interfaces, such as PCI Express interface, USB 3.0 interface and SATA interface are widely used in today's computer system for satisfying such high bandwidth demands. For example, the first generation PCI Express provides at least 2.5 Gbps for each lane; USB 3.0 offers at least 5.0 Gbps for each port; and SATA has at least 1.5 Gbps capacity for each port. Those serial interfaces utilize higher operational clocks and apply more data lanes/ports to improve data transmission efficiency, which greatly enhance performance of computer systems.
Serial interface devices, USB 3.0 devices for instance, coupled to a serial bus, a USB 3.0 bus for instance, usually being operated at a high-speed transmission where data volume is large. In order to make sure the accuracy of data transmission, a conventional built-in self test (BIST) circuit is used to test the serial interface device. A test pattern generator (TPG) and an output response analysis (ORA) are built-in to a port under test. Please refer to FIG. 1. FIG. 1 illustrates architecture of conventional built-in self test circuit 100. The built-in self test circuit 100 includes a pattern generator 102, an elastic buffer 104, a pattern register 106, a pattern comparison module 108, and a port under test 110. The pattern generator 102 generates a test pattern to the port under test 110 and the pattern register 106, then the elastic buffer 104 receives and transmits the test patterns via the port under test 110 to the pattern comparison module 108, and the pattern register 106 temporarily stores and transmits the test patterns in a predetermined time to the pattern comparison module 108. The test pattern received by the elastic buffer 104 and the test pattern stored in the pattern register 106 are compared; the pattern comparison module 108 determines whether the port under test 110 correctly transmits the test pattern generated by the pattern generator 102.
The conventional built-in self test circuit 100 does not require an external automatically test equipment (ATE) to generate a test vector, also it is not required by the ATE to analyze test results. Therefore the test bandwidth requirement is less than general test methods, and test speed is not limited by the ATE speed hence it is more efficient. However, the port under test 110 of serial interface device such as USB 3.0 device includes a plurality of loopback paths, which also means that time required by the test patterns to pass through the port under test 110 is not constant, so that the loopback latency cannot be predicted. Therefore the storage capacity of the pattern register 106 must be sufficiently large to compensate the loopback latency. Furthermore, the built-in self test circuit 100 will be affected by phase jitter which causes errors in the pattern comparison module 108. Moreover, the storage capacity of the pattern register 106 must be restricted; therefore when the loopback latency becomes too great, the built-in self test architecture 100 will not operate accurately.